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Chemical and structural analysis on magnetic tunnel junctions using a decelerated scanning electron beam.


ABSTRACT: Current information technology relies on the advancement of nanofabrication techniques. For instance, the latest computer memories and hard disk drive read heads are designed with a 12?nm node and 20?nm wide architectures, respectively. With matured nanofabrication processes, a yield of such nanoelectronic devices is typically up to about 90%. To date the yield has been compensated with redundant hardware and software error corrections. In the latest memories, approximately 5% redundancy and parity bits for error corrections are used, which increase the total production cost of the devices. This means the yield directly affects the device costs. It is hence critical to increase the yield in nanofabrication. In this paper, we have applied our recently developed method to image buried interfaces in combination with chemical analysis to evaluate magnetic tunnel junctions and have revealed their different magnetoresistance ratios caused by the presence of materials formed at the junction edges. The formation of these materials can be avoided by optimising the junction patterning process to remove residual carbon introduced from resist. Our imaging method with chemical analysis have demonstrated a significant potential for the improvement of junction performance, resulting in higher yields. This can be used as a quality assurance tool in a nanoelectronic device production line.

SUBMITTER: Jackson E 

PROVIDER: S-EPMC5954102 | biostudies-literature | 2018 May

REPOSITORIES: biostudies-literature

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Chemical and structural analysis on magnetic tunnel junctions using a decelerated scanning electron beam.

Jackson Edward E   Sun Mingling M   Kubota Takahide T   Takanashi Koki K   Hirohata Atsufumi A  

Scientific reports 20180515 1


Current information technology relies on the advancement of nanofabrication techniques. For instance, the latest computer memories and hard disk drive read heads are designed with a 12 nm node and 20 nm wide architectures, respectively. With matured nanofabrication processes, a yield of such nanoelectronic devices is typically up to about 90%. To date the yield has been compensated with redundant hardware and software error corrections. In the latest memories, approximately 5% redundancy and par  ...[more]

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