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Sputtered Electrolyte-Gated Transistor with Temperature-Modulated Synaptic Plasticity Behaviors.

ABSTRACT: Temperature has always been considered as an essential factor for almost all kinds of semiconductor-based electronic components. In this work, temperature-dependent synaptic plasticity behaviors, which are mimicked by the indium-gallium-zinc oxide thin-film transistors gated with sputtered SiO₂ electrolytes, have been studied. With the temperature increasing from 303 to 323 K, the electrolyte capacitance decreases from 0.42 to 0.11 μF cm^-2. The mobility increases from 1.4 to 3.7 cm² V^-1 s^-1, and the threshold voltage negatively shifts from -0.23 to -0.51 V. Synaptic behaviors under both a single pulse and multiple pulses are employed to study the temperature dependence. With the temperature increasing from 303 to 323 K, the post-synaptic current (PSC) at the resting state increases from 1.8 to 7.3 μA. Under a single gate pulse of 1 V and 1 s, the PSC signal altitude and the PSC retention time decrease from 2.0 to 0.7 μA and 5.1 × 10² to 2.5 ms, respectively. A physical model based on the electric field-induced ion drifting, ionic-electronic coupling, and gradient-coordinated ion diffusion is proposed to understand these temperature-dependent synaptic behaviors. Based on the experimental data on individual transistors, temperature-modulated pattern learning and memorizing behaviors are conceptually demonstrated. The in-depth investigation of the temperature dependence helps pave the way for further electrolyte-gated transistor-based neuromorphic applications.

SUBMITTER: Fu YM

PROVIDER: S-EPMC9245437 | biostudies-literature |

REPOSITORIES: biostudies-literature

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Project description:Organic synaptic transistors are a promising technology for advanced electronic devices with simultaneous computing and memory functions and for the application of artificial neural networks. In this study, the neuromorphic electrical characteristics of organic synaptic electrolyte-gated transistors are correlated with the microstructural and interfacial properties of the active layers. This is accomplished by utilizing a semiconducting/insulating polyblend-based pseudobilayer with embedded source and drain electrodes, referred to as PB-ESD architecture. Three variations of poly(3-hexylthiophene) (P3HT)/poly(methyl methacrylate) (PMMA) PB-ESD-based organic synaptic transistors are fabricated, each exhibiting distinct microstructures and electrical characteristics, thus serving excellent samples for exploring the critical factors influencing neuro-electrical properties. Poor microstructures of P3HT within the active layer and a flat active layer/ion-gel interface correspond to typical neuromorphic behaviors such as potentiated excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and short-term potentiation (STP). Conversely, superior microstructures of P3HT and a rough active layer/ion-gel interface correspond to significantly higher channel conductance and enhanced EPSC and PPF characteristics as well as long-term potentiation behavior. Such devices were further applied to the simulation of neural networks, which produced a good recognition accuracy. However, excessive PMMA penetration into the P3HT conducting channel leads to features of a depressed EPSC and paired-pulse depression, which are uncommon in organic synaptic transistors. The inclusion of a second gate electrode enables the as-prepared organic synaptic transistors to function as two-input synaptic logic gates, performing various logical operations and effectively mimicking neural modulation functions. Microstructure and interface engineering is an effective method to modulate the neuromorphic behavior of organic synaptic transistors and advance the development of bionic artificial neural networks.

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Sputtered Electrolyte-Gated Transistor with Temperature-Modulated Synaptic Plasticity Behaviors.

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