High Performance and Low power Monolithic Three-Dimensional Sub-50?nm Poly Si Thin film transistor (TFTs) Circuits.

ABSTRACT: Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50?nm TFTs-based MOSFETs with ON-current (I_on)/subthreshold swing (S.S.) of 181?µA/µm/107?mV/dec and 188?µA/µm/98?mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390?mV at V_DD?=?1.0?V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.

SUBMITTER: Wu TT 

PROVIDER: S-EPMC5431052 | biostudies-literature | 2017 May

REPOSITORIES: biostudies-literature