Browse
Submit Data
Databases
API
Help

Dataset Information

25 Views

0 Connections

0 Citations

0 Reanalyses

0 Downloads

Omics score: 0

Remarkably High-Performance Nanosheet GeSn Thin-Film Transistor.

ABSTRACT: High-performance p-type thin-film transistors (pTFTs) are crucial for realizing low-power display-on-panel and monolithic three-dimensional integrated circuits. Unfortunately, it is difficult to achieve a high hole mobility of greater than 10 cm²/V·s, even for SnO TFTs with a unique single-hole band and a small hole effective mass. In this paper, we demonstrate a high-performance GeSn pTFT with a high field-effect hole mobility (μ_FE), of 41.8 cm²/V·s; a sharp turn-on subthreshold slope (SS), of 311 mV/dec, for low-voltage operation; and a large on-current/off-current (I_ON/I_OFF) value, of 8.9 × 10⁶. This remarkably high I_ON/I_OFF is achieved using an ultra-thin nanosheet GeSn, with a thickness of only 7 nm. Although an even higher hole mobility (103.8 cm²/V·s) was obtained with a thicker GeSn channel, the I_OFF increased rapidly and the poor I_ON/I_OFF (75) was unsuitable for transistor applications. The high mobility is due to the small hole effective mass of GeSn, which is supported by first-principles electronic structure calculations.

SUBMITTER: Yen TJ

PROVIDER: S-EPMC8777649 | biostudies-literature |

REPOSITORIES: biostudies-literature

ACCESS DATA

Json Xml

Similar Datasets

Remarkably High Mobility Thin-Film Transistor on Flexible Substrate by Novel Passivation Material.

Project description:High mobility thin-film transistor (TFT) is crucial for future high resolution and fast response flexible display. Remarkably high performance TFT, made at room temperature on flexible substrate, is achieved with record high field-effect mobility (μ FE ) of 345 cm2/Vs, small sub-threshold slope (SS) of 103 mV/dec, high on-current/off-current (I ON /I OFF ) of 7 × 106, and a low drain-voltage (VD) of 2 V for low power operation. The achieved mobility is the best reported data among flexible electronic devices, which is reached by novel HfLaO passivation material on nano-crystalline zinc-oxide (ZnO) TFT to improve both I ON and I OFF . From X-ray photoelectron spectroscopy (XPS) analysis, the non-passivated device has high OH-bonding intensity in nano-crystalline ZnO, which damage the crystallinity, create charged scattering centers, and form potential barriers to degrade mobility.

| S-EPMC5430887 | biostudies-literature

Remarkably high mobility ultra-thin-film metal-oxide transistor with strongly overlapped orbitals.

Project description:High mobility channel thin-film-transistor (TFT) is crucial for both display and future generation integrated circuit. We report a new metal-oxide TFT that has an ultra-thin 4.5 nm SnO2 thickness for both active channel and source-drain regions, very high 147 cm(2)/Vs field-effect mobility, high ION/IOFF of 2.3 × 10(7), small 110 mV/dec sub-threshold slope, and a low VD of 2.5 V for low power operation. This mobility is already better than chemical-vapor-deposition grown multi-layers MoS2 TFT. From first principle quantum-mechanical calculation, the high mobility TFT is due to strongly overlapped orbitals.

| S-EPMC4705631 | biostudies-other

Remarkably High Hole Mobility Metal-Oxide Thin-Film Transistors.

Project description:High performance p-type thin-film transistor (p-TFT) was realized by a simple process of reactive sputtering from a tin (Sn) target under oxygen ambient, where remarkably high field-effect mobility (? FE ) of 7.6?cm2/Vs, 140?mV/dec subthreshold slope, and 3?×?104 on-current/off-current were measured. In sharp contrast, the SnO formed by direct sputtering from a SnO target showed much degraded ? FE , because of the limited low process temperature of SnO and sputtering damage. From the first principle quantum-mechanical calculation, the high hole ? FE of SnO p-TFT is due to its considerably unique merit of the small effective mass and single hole band without the heavy hole band. The high performance p-TFTs are the enabling technology for future ultra-low-power complementary-logic circuits on display and three-dimensional brain-mimicking integrated circuits.

| S-EPMC5772488 | biostudies-other

Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer.

Project description:Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (?FE) and large on-current/off-current (ION/IOFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high ?FE of 4.4 cm2/Vs, large ION/IOFF of 1.2 × 105, and sharp transistor's turn-on subthreshold slopes (SS) of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO2/SnO interface and related ?FE were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn-O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO2 to demote the device performance. The hole ?FE, ION/IOFF, and SS values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.

| S-EPMC7823917 | biostudies-literature

Li-Assisted Low-Temperature Phase Transitions in Solution-Processed Indium Oxide Films for High-Performance Thin Film Transistor.

Project description:Lithium (Li)-assisted indium oxide (In2O3) thin films with ordered structures were prepared on solution-processed zirconium oxide (ZrO2) gate dielectrics by spin-casting and thermally annealing hydrated indium nitrate solutions with different Li nitrate loadings. It was found that the Li-assisted In precursor films on ZrO2 dielectrics could form crystalline structures even at processing temperatures (T) below 200?°C. Different In oxidation states were observed in the Li-doped films, and the development of such states was significantly affected by both temperature and the mol% of Li cations, [Li(+)]/([In(3+)]?+?[Li(+)]), in the precursor solutions. Upon annealing the Li-assisted precursor films below 200?°C, metastable indium hydroxide and/or indium oxyhydroxide phases were formed. These phases were subsequently transformed into crystalline In2O3 nanostructures after thermal dehydration and oxidation. Finally, an In2O3 film doped with 13.5?mol% Li(+) and annealed at 250?°C for 1?h exhibited the highest electron mobility of 60?cm(2) V(-1) s(-1) and an on/off current ratio above 10(8) when utilized in a thin film transistor.

| S-EPMC4848541 | biostudies-literature

High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits.

Project description:Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/µm/107 mV/dec and 188 µA/µm/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at VDD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.

| S-EPMC5431052 | biostudies-literature

Fully solution-processed flexible organic thin film transistor arrays with high mobility and exceptional uniformity.

Project description:Printing fully solution-processed organic electronic devices may potentially revolutionize production of flexible electronics for various applications. However, difficulties in forming thin, flat, uniform films through printing techniques have been responsible for poor device performance and low yields. Here, we report on fully solution-processed organic thin-film transistor (TFT) arrays with greatly improved performance and yields, achieved by layering solution-processable materials such as silver nanoparticle inks, organic semiconductors, and insulating polymers on thin plastic films. A treatment layer improves carrier injection between the source/drain electrodes and the semiconducting layer and dramatically reduces contact resistance. Furthermore, an organic semiconductor with large-crystal grains results in TFT devices with shorter channel lengths and higher field-effect mobilities. We obtained mobilities of over 1.2?cm(2) V(-1) s(-1) in TFT devices with channel lengths shorter than 20??m. By combining these fabrication techniques, we built highly uniform organic TFT arrays with average mobility levels as high as 0.80?cm(2) V(-1) s(-1) and ideal threshold voltages of 0?V. These results represent major progress in the fabrication of fully solution-processed organic TFT device arrays.

| S-EPMC3912504 | biostudies-literature

Modulating Thin Film Transistor Characteristics by Texturing the Gate Metal.

Project description:The development of reliable, high performance integrated circuits based on thin film transistors (TFTs) is of interest for the development of flexible electronic circuits. In this work we illustrate the modulation of TFT transconductance via the texturing of the gate metal created by the addition of a conductive pattern on top of a planar gate. Texturing results in the semiconductor-insulator interface acquiring a non-planar geometry with local variations in the radius of curvature. This influences various TFT parameters such as the subthreshold slope, gate voltage at the onset of conduction, contact resistance and gate capacitance. Specific studies are performed on textures based on periodic striations oriented along different directions. Textured TFTs showed upto ±40% variation in transconductance depending on the texture orientation as compared to conventional planar gate TFTs. Analytical models are developed and compared with experiments. Gain boosting in common source amplifiers based on textured TFTs as compared to conventional TFTs is demonstrated.

| S-EPMC5738405 | biostudies-literature

High-mobility ZrInO thin-film transistor prepared by an all-DC-sputtering method at room temperature.

Project description:Thin-film transistors (TFTs) with zirconium-doped indium oxide (ZrInO) semiconductor were successfully fabricated by an all-DC-sputtering method at room temperature. The ZrInO TFT without any intentionally annealing steps exhibited a high saturation mobility of 25.1 cm(2)V(-1)s(-1). The threshold voltage shift was only 0.35 V for the ZrInO TFT under positive gate bias stress for 1 hour. Detailed studies showed that the room-temperature ZrInO thin film was in the amorphous state with low carrier density because of the strong bonding strength of Zr-O. The room-temperature process is attractive for its compatibility with almost all kinds of the flexible substrates, and the DC sputtering process is good for the production efficiency improvement and the fabrication cost reduction.

| S-EPMC4846996 | biostudies-literature

A Sputtered Silicon Oxide Electrolyte for High-Performance Thin-Film Transistors.

Project description:Low operating voltages have been long desired for thin-film transistors (TFTs). However, it is still challenging to realise 1-V operation by using conventional dielectrics due to their low gate capacitances and low breakdown voltages. Recently, electric double layers (EDLs) have been regarded as a promising candidate for low-power electronics due to their high capacitance. In this work, we present the first sputtered SiO2 solid-state electrolyte. In order to demonstrate EDL behaviour, a sputtered 200 nm-thick SiO2 electrolyte was incorporated into InGaZnO TFTs as the gate dielectric. The devices exhibited an operating voltage of 1 V, a threshold voltage of 0.06 V, a subthreshold swing of 83 mV dec-1 and an on/off ratio higher than 105. The specific capacitance was 0.45 µF cm-2 at 20 Hz, which is around 26 times higher than the value obtained from thermally oxidised SiO2 films with the same thickness. Analysis of the microstructure and mass density of the sputtered SiO2 films under different deposition conditions indicates that such high capacitance might be attributed to mobile protons donated by atmospheric water. The InGaZnO TFTs with the optimised SiO2 electrolyte also showed good air stability. This work provides a new pathway to the realisation of high-yield low-power electronics.

| S-EPMC5429786 | biostudies-literature

OmicsDI is part of the ELIXIR infrastructure

OmicsDI is an Elixir interoperability service. Learn more ›

OmicsDI Databases

PRIDE
PeptideAtlas
MassIVE
JPOST Repository
Physiome Model Repository

EGA
EVA
ENA
LINCS
PAXDB
Cell Collective

MetaboLights
Metabolomics Workbench
MetabolomeExpress
GNPS
BioModels
FAIRDOMHub

ArrayExpress
dbGaP
ExpressionAtlas
GEO
NODE

Information

Databases
Help
API
Contact us
Code on GitHub
Terms of use
Submit Data