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Integration scheme of nanoscale resistive switching memory using bottom-up processes at room temperature for high-density memory applications.

ABSTRACT: A facile and versatile scheme is demonstrated to fabricate nanoscale resistive switching memory devices that exhibit reliable bipolar switching behavior. A solution process is used to synthesize the copper oxide layer into 250-nm via-holes that had been patterned in Si wafers. Direct bottom-up filling of copper oxide can facilitate fabrication of nanoscale memory devices without using vacuum deposition and etching processes. In addition, all materials and processes are CMOS compatible, and especially, the devices can be fabricated at room temperature. Nanoscale memory devices synthesized on wafers having 250-nm via-holes showed reproducible resistive switching programmable memory characteristics with reasonable endurance and data retention properties. This integration strategy provides a solution to overcome the scaling limit of current memory device fabrication methods.

SUBMITTER: Han UB

PROVIDER: S-EPMC4929478 | biostudies-literature | 2016 Jul

REPOSITORIES: biostudies-literature

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Integration scheme of nanoscale resistive switching memory using bottom-up processes at room temperature for high-density memory applications.

Han Un-Bin UB Lee Jang-Sik JS

Scientific reports 20160701

A facile and versatile scheme is demonstrated to fabricate nanoscale resistive switching memory devices that exhibit reliable bipolar switching behavior. A solution process is used to synthesize the copper oxide layer into 250-nm via-holes that had been patterned in Si wafers. Direct bottom-up filling of copper oxide can facilitate fabrication of nanoscale memory devices without using vacuum deposition and etching processes. In addition, all materials and processes are CMOS compatible, and espec ...[more]

PMID: 27364856

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