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A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process.

ABSTRACT: This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique self-inhibit operation onto the resistive random access memory (RRAM) load, achieving zero static power during data hold.

SUBMITTER: Hsu MY

PROVIDER: S-EPMC5472634 | biostudies-other | 2017 Dec

REPOSITORIES: biostudies-other

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A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process.

Hsu Meng-Yin MY Liao Chu-Feng CF Shih Yi-Hong YH Lin Chrong Jung CJ King Ya-Chin YC

Nanoscale research letters 20170615 1

This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique s ...[more]

PMID: 28622720

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